Method of creating shielded structures to protect semiconductor devices

ABSTRACT

An apparatus on a wafer, comprising; a first metal layer of a wall, a second metal layer of the wall, a third metal layer of the wall comprising; one or more base frames, a fourth metal layer of the wall comprising; one or more vertical frame pairs each on top of the one or more base frames and having a pass-thru therein, a fifth metal layer of the wall comprising; one or more top frames each over the pass-thru; and a metal lid.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to the field of semiconductordevice fabrication, and more specifically to a method and structure forconstructing a structure using semiconductor device fabrication methodsthat shields semiconductor devices.

[0003] 2. Discussion of Related Art

[0004] Today integrated circuits are made up of literally millions ofactive and passive devices such as transistors, capacitors, andresistors. In order to improve overall chip performance, some devicesmay need to be shielded from the electromagnetic interference (EMI) fromadjacent devices, from heat, and from light.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005]FIG. 1 is an illustration of a Faraday cage with insulatedpass-thrus;

[0006]FIG. 2 is an illustration of a semiconductor device on a siliconwafer;

[0007]FIGS. 3a & b are illustrations of a deposition of a firstdielectric layer onto a silicon substrate and a semiconductor device;

[0008]FIGS. 4a, b are illustrations of a photoresist layer on the firstlayer dielectric;

[0009]FIGS. 5a & b are illustrations of via openings and a first slot;

[0010]FIGS. 6a & b are illustrations of a first conducting layer;

[0011]FIGS. 7a & b are illustrations of a deposit of a first conductinglayer and a first layer of a wall;

[0012]FIGS. 8a & b are illustrations of a metal one layer;

[0013]FIGS. 9a & b are illustrations of a first interconnect layer and asecond layer of the wall;

[0014]FIGS. 10a & b are illustrations of a second dielectric layer;

[0015]FIGS. 11a & b are illustrations of via a second dielectric layerwith via openings, a third wall slot, and a base frame;

[0016]FIGS. 12a & b are illustrations a second conductive layerdeposited;

[0017]FIGS. 13a & b are illustrations of a metal two layer deposited;

[0018]FIGS. 14a & b are illustrations of a second layer interconnect, afourth layer of the wall, vertical frame slots, and a pass-thru;

[0019]FIGS. 15a & b are illustrations of a third dielectric layer;

[0020]FIGS. 16a & b are illustrations of a fifth slot, and a top frame;

[0021]FIGS. 17a & b are illustrations of a third conductive layercompleting a fifth layer of the wall;

[0022]FIGS. 18a & b are illustrations of a barrier coating on the lid;

[0023]FIGS. 19a & b is an illustration of another embodiment havingfurther layering;

[0024]FIG. 20 is an illustration another embodiment having pairs ofinsulated pass-thrus;

[0025]FIG. 21 is an illustration of another embodiment having two pairof insulated pass-thrus;

[0026]FIG. 22 is an illustration of a pass-thru partially insulated withair.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

[0027] A novel device structure and method for shielding a region on asemiconductor is described. In the following description numerousdetails are set forth such as specific materials and processes in orderto provide a thorough understanding of the present invention. In otherinstances, well known semiconductor processing techniques and machineryhave not been set forth in detail to avoid obscuring the presentinvention.

[0028] The present invention is a novel device structure and method forshielding individual or a selection of semiconductor devices fromconductive and/or radiated energy. Such as, for example, electromagneticinterference (EMI) from radiation originating outside the semiconductoror from adjacent devices on the semiconductor. The present invention maybe also used to direct thermal energy relative to a semiconductor, or toshield a semiconductor from light.

[0029] In an embodiment, a Faraday cage is constructed on a siliconsubstrate, and encloses one or more semiconductor devices within astructure of metal. The semiconductor devices having input/output leadsor pass-thrus that pass through the Faraday cage walls at one or moreinsulated locations.

[0030] The embodiment provides that interconnects and vias both insideand outside the disclosed Faraday cage may also be constructed in thesame layers used to construct the Faraday cage.

[0031] To construct the Faraday cage with insulated pass-thrus, vias andinterconnects, alternating layers of tungsten (W) and aluminum (Al) areused. The use of tungsten (conductive metal) will fill in via openingsbetween interconnects to create plugs or filled vias. This tungstenlayer will add metal layers to the Faraday cage wall(s) at the sametime. Alternating with the tungsten layers, interconnects are etchedfrom layers of aluminum or aluminum alloy. As with the tungsten layers,each aluminum layer will also add a layer in constructing the walls ofthe Faraday cage. Left within layers of the metal Faraday cage walls arepieces of dielectric material that will make up the insulation framework(frame) around each pass-thru. This insulation surrounds or frames eachpass-thru lead at the point where it passes through the metal Faradaycage wall. For each pass-thru insulation or frame construction, onemetal layer will have one horizontal block (base frame), the next metallayer will have one pair of vertical bars (vertical frame pairs), andfinally the insulation will be complete with the next layer addition ofanother horizontal bar (top frame). However it is possible for multipleinsulated pass-thrus to share common frame components.

[0032] The process of depositing layers of dielectric and metal,positive or negative photoresist and etching the layers to form vias andinterconnects is well understood. In addition, at the same time for thisembodiment, trenches (slots) will be etched in dielectric around thesemiconductor device(s) to be enclosed by the Faraday cage. The slotswill be filled with tungsten. Alternating the tungsten layers are layersof aluminum. These will be etched to add more layers to the Faraday cagewalls and at the same time construct the interconnects. Finally a lastmetal layer will completely cover the area enclosed by the Faraday cagewall(s) to act as a roof or lid over the walls.

[0033] The following embodiment will describe the process of jointfabrication of the Faraday cage, enclosing with metal, one or moresemiconductor devices having insulated pass-thrus (input/output leads orconductors) and layers of interconnects joined by vias to thesemiconductor devices.

[0034] Referring to FIG. 1, cross-sections A-A and B-B will be shown asfigure a and figure b designations respectively in later illustrations.These cross-sections (A-A & B-B) appear throughout many of the figuresto show a simultaneous construction of the Faraday cage walls 102 (B-B)with the vias (shown after FIG. 2) (A-A) and the interconnects 108(A-A). Although FIG. 1 shows the construction of two pass-thru leads(pass-thrus) 108 and insulators 106 at the front and back walls 102, thelater figures only illustrate construction of a single pass-thru 108 anda single insulator 106. This is done for clarity, however it is to beunderstood that any number of pass-thrus 108 and insulators 106 may befabricated in a Faraday cage 100 at different levels.

[0035] As shown in FIG. 2, prior to beginning depositions for Faradaycage 100 (FIG. 1) construction, the semiconductor device 104 such as anMOS transistor having a gate 103 with a gate oxide beneath 106, and apair of source and drain regions 105, have been constructed on a wafersubstrate (substrate) 101. The substrate may be made from such materialsas silicon (Si), gallium arsenide (GaAs), or one of thesilicon-on-insulator (SOI) materials such as silicon-on-sapphire (SOS)or silicon-on-diamond. The transistor may link with other transistors tofunction in a variety of tasks such as a resister, capacitor, memorystorage device, sense amp, or an input/output buffer.

[0036] Turning to FIGS. 3a & b, a first coating of the dielectric 120(first dielectric layer) is deposited as an insulative layer over thesubstrate 101 and the previously fabricated semiconductor device 104.The dielectric material for this embodiment is silicon dioxide (SiO₂)but may also be silicon nitride (Si₃N₄), phosphorus-doped silicon oxide(PSG), or boron/phosphorus-doped silicon oxide (BPSG).

[0037] A process known as patterning is next performed. This involvesapplying a photoresist coating over the substrate and then using wellknown photolithography steps such as masking, exposing, and developing,to form a patterned photoresist layer. The underlying material is thenetched in alignment with the patterned photoresist layer. As shown inFIGS. 4a & b, the first dielectric layer 120 is coated with thephotoresist layer 123 within which is formed a pattern 123. The pattern123 in the photoresist is reacted and the non-reacted photoresistmaterial is then removed.

[0038] The next step is an etch of the first dielectric layer 120 thatfollows the shape of the photoresist pattern 123. With this etch, thephotoresist layer protects the dielectric layer 120 beneath from theetch operation. Referring to FIG. 5a, first via openings 126 are etchedwithin the first dielectric layer 120. These first via openings 126 areetched through the first dielectric layer 120 exposing a portion of thesemiconductor 104 surface. Turning now to FIG. 5b, at the same time afirst slot 124 is etched in the first dielectric layer 120, andsurrounds the semiconductor device(s) 104 (FIG. 5a) to be EMI shielded.The first slot 124 begins the formation of the Faraday cage walls 102(FIG. 1). This etch and subsequent etches may be accomplished by avariety of methods such as with a wet chemical (wet-chem) or by one ofthe plasma etches such as a reactive ion etch.

[0039] Next, but not shown, a barrier coating may be applied to theetched dielectric 120 surface to improve adhesion between a metalcoating to be next applied and the dielectric 120. This coating may betitanium or titanium nitride material. This barrier coating may be usedon any dielectric surface when a metal coating will be applied over thedielectric.

[0040] Now, a fill layer of a material (first conducting layer) 125 isdeposited as shown in FIGS. 6a & b. Turning now to FIGS. 7a & b, thereis seen the first conducting layer 125 after it has been polished backto the first dielectric layer 120. This polish is accomplished by achemical etch and a chemical-mechanical polish (CMP) may be used priorto the chemical etch. The first conducting layer 125 has filled in thevia openings 126 (FIG. 5a) forming vias 127 (filled vias, via plugs, orplugs) and filled in the first slot 124 (FIG. 5b) to form a first layerof wall 128 in constructing the Faraday cage walls 102 (FIG. 1). Theconducting material used to fill in the vias for this embodiment istungsten (W) but may be another metal such aluminum (Al) or a non-metalsuch as polysilicon (Si).

[0041] Referring now to FIGS. 8a & b, a first metal layer or metal one(Ml) 130 of aluminum (Al) is deposited over the dielectric top surface228. While the metal layers for this embodiment are made of aluminum,other well known metals used for interconnects, such as copper, may beused.

[0042] Turning to FIGS. 9a & b are displayed the after-patterningresults. A first layer of interconnects (first interconnects) 225 areformed in the M1 130. At the same time with M1 130, a second layer ofthe wall 224 is placed over the first layer of the wall 125 that isforming the overall wall structure 102 (FIG. 1).

[0043] Referring now to FIGS. 10a & b, there is seen a deposit of asecond dielectric (SiO₂) layer 220. This second dielectric layer 220fills in around the second layer of the wall 224 construction and thefirst layer of interconnects 225.

[0044] The second dielectric (SiO2) layer 220 is patterned(photoresist+etch) as described above but not shown here. The results ofthe patterning is displayed in FIGS. 11a & b. Via openings 226 areetched until surfaces on the first interconnects 225 are exposed. Inaddition, a second slot 324 is constructed within the second dielectriclayer 220 and positioned above the first and second layers of wall 125,224. At a selected location, the second slot 324 construction leaves abase frame 350 within, of dielectric (from second SiO₂ layer 220), tobegin construction of the pass-thru insulation 106 (FIG. 1).

[0045] Referring now to FIGS. 12a & b, a second fill layer of tungsten(second conducting material) is deposited and then polished back to thesecond dielectric layer 220. After polish, a tungsten filled third layerof the wall 326 remains over the previously constructed walls 125, 224.At the same time, vias 227 are created. In addition, the tungsten layer326 fills in around the base frame 350.

[0046]FIGS. 13a & b show a deposit of a second metal layer or metal two(M2) 230 of aluminum. After deposition, the M2 230 is patterned asdescribed above.

[0047] Turning now to FIGS. 14a & b, after etching, a second layer ofinterconnects 325 (second interconnects) are formed from M2. At the sametime, a fourth layer of the wall 424 is formed from M2 that ispositioned over the previously constructed layers of wall 125, 224, 326.Additionally, within the fourth layer of the wall 424 there remain twovertical spaces (vertical frame slots) 360 over each base frame 350.Above the base frame 350 and between the two vertical frame slots 360passes the pass-thru 380 from the interconnects 325 to circuitry outsidethe partially constructed wall 102 (FIG. 1).

[0048] At this point (FIGS. 14a & b), there is constructed inalternating tungsten and aluminum, four layers of the partiallyconstructed wall 125, 224, 326, 424. The metal (Al) pass-thru lead 380connects from the second interconnect 325 and passes through thepartially constructed insulator 350, 360 to outside circuitry (notshown).

[0049] Referring now to FIGS. 15a & b, a third dielectric (SiO₂) layer320 is deposited. The third SiO₂ layer 320 fills in the vertical frameslots 360 (FIG. 14b) to form the vertical frame pairs 361 and later thetop frame 550 (shown in FIG. 16b later) of the insulator 106 (FIG. 1).

[0050] The next patterning operation is not shown but uses thetechniques described above with the results shown in FIGS. 16a & b. Thethird dielectric 320 layer is patterned to form a third slot 524 abovethe previous layers of wall 125, 224, 326, 424. Within the third slot524 is formed the top frame 550 (SiO₂) over the vertical frame pairs 361(SiO₂). The pass-thru is now enclosed with insulation (SiO₂) at the wall125, 224, 326, 424. In addition, via openings if needed may be createdthat expose surfaces on the interconnects 325 beneath.

[0051] Turning now to FIGS. 17a & b, a third fill layer of tungsten(third conducting layer) (not shown) is deposited and then polished backto the third dielectric layer 320. The third fill layer fills in thethird slot 524 (FIG. 16b) to form the fifth layer of the wall.

[0052] Referring now to FIGS. 18a & b, a metal layer (M3) 330 ofaluminum is deposited to form the lid 560 to complete the enclosure ofthe semiconductor(s) (not shown). The ML3 330 may be patterned (notshown) to shape the lid 560 or add other interconnect circuitry (notshown) and completes the basic construction of the Faraday cage 100(FIG. 1). The lid 560 now covers the walls 102 (FIG. 1) and the entirearea contained within the walls 102 (FIG. 1). Afterward, a last coatingof dielectric 510 may be deposited to place a barrier coating or sealanton the lid 560.

[0053] Referring to FIGS. 19a & b, there is shown an embodiment havingmore layers added to create another interconnect layer 425 and vias notshown here may be fabricated connecting the lid 460 to otherinterconnects below. There is also seen two pair of insulated pass-thrus400. Here, the two pair of insulated pass-thrus 400 are constructed ondiffering layers or levels. In this illustration, the individualinsulated pass-thrus 400 and pass-thru pairs 400 are separated from eachother by dielectric material 402.

[0054] Turning to FIG. 20 is shown a pair of insulated pass-thrus 502separated by both dielectric material 504 and metal material 506.

[0055] Referring to FIG. 21 is seen two pair of insulated pass-thrus 604each on a different level and separated within each insulated pass-thrupair 604 and between pass-thru pairs 604 by both dielectric 604 andmetal 606 material.

[0056] In FIG. 22 is illustrated an insulated pass-thru 702 in which thepass-thru lead 702 is supported by a dielectric material 706 but thevertical frame pairs 703 and the top frame 704 are spaces (voids) filledwith air.

[0057] It should also be understood that any number of layers ofinsulation or metal layers, M1, M2, M3 (metal four, metal five, etc.)may be used to construct multiple pass-thrus on a single level andmultiple levels of interconnects and pass-thrus. In addition, for otherembodiments, the metal layer deposited to form the lid in the disclosedembodiment may be patterned into interconnect circuitry for devicesoutside the Faraday cage.

[0058] Further, for other embodiments, there may be subsequent layersdeposited above a Faraday cage lid to add interconnects, vias, and otherFaraday cage walls to circuitry stacked outside and/or higher than agiven Faraday cage.

[0059] This method of forming the Faraday cage could be employed toconstruct structures for other applications such as to redirectelectrostatic discharge, to distribute thermal energy, or to shieldlight sensitive devices such as, for example, might be used in opticalswitching.

We claim:
 1. An apparatus on a wafer, comprising: a first metal layer ofa wall; a second metal layer of the wall; a third metal layer of thewall comprising: one or more base frames; a fourth metal layer of thewall comprising: one or more vertical frame pairs each on top of the oneor more base frames and having a pass-thru therein; a fifth metal layerof the wall comprising: one or more top frames each over the pass-thru;and a metal lid.
 2. The apparatus on a wafer of claim 1, wherein: thefourth metal layer comprises one or more base frames; the fifth metallayer of the wall comprising one or more vertical frame pairs each ontop of the one or more base frames and having a pass-thru therein; asixth metal layer of the wall comprising: one or more top frames overeach pass-thru; and a metal lid.
 3. An apparatus on a wafer, comprising:a first layer of a wall made of a first metal; a second layer of thewall made of a second metal; a third layer of the wall made of the firstmetal and comprising: one or more base frames; a fourth layer of thewall made of the second metal comprising: one or more vertical framepairs around one or more pass-thrus; a fifth layer of the wall made ofthe second metal comprising: one or more top frames; and a lid.
 4. Theapparatus on a wafer of claim 3, wherein; one or more of the verticalframe pairs; and one or more of the top frames are voids filled withair.
 5. The apparatus on a wafer of claim 3, further wherein; the fourthlayer of the wall is comprised of one or more base frames; the fifthlayer of the wall is comprised of the first metal and having one or morevertical frame pairs around one or more pass-thrus; a sixth layer of thewall made of the second metal and comprising one or more top frames eachover the pass-thru and a lid.
 6. The apparatus on a wafer of claim 5,wherein; one or more of the vertical frame pairs; and one or more of thetop frames are voids filled with air.
 7. An apparatus on a wafer,comprising: a first layer of a wall made of a first conductive materialaround one or more semiconductor devices; a second layer of the wall,positioned over the first layer, and made of metal one; a third layer ofthe wall positioned over the second layer of the wall, made of a secondconductive material, within which exists one or more base frames; afourth layer of the wall, positioned over the third layer of the wall,made of metal two, within which exists one or more pass-thrus eachsurrounded by a vertical frame pair and the base frame; a fifth layer ofthe wall, positioned over the fourth layer of the wall, made of metalthree, within which exists a top frame above the one or more pass-thrus,and; a lid of metal three positioned over the fifth layer of the wall.8. The apparatus on a wafer of claim 7, wherein, the lid is covered witha protective layer.
 9. The apparatus on a wafer of claim 8, wherein, theprotective layer is a dielectric material.
 10. The apparatus on a waferof claim 7, wherein; one or more of the vertical frame pairs; and one ormore of the top frames are voids filled with air.
 11. A method ofconstructing an apparatus on a wafer, comprising: depositing andpatterning a first dielectric layer over one or more semiconductordevices comprising: a first slot surrounding the one or moresemiconductor devices; depositing and polishing a first conductivematerial comprising: a first layer of a wall; depositing and patterninga metal one layer comprising: a second layer of the wall positioned overthe first layer of the wall; depositing and patterning a seconddielectric layer comprising: a second slot positioned over the secondlayer of wall, and one or more base frames within the second slot;depositing and polishing a second conductive material comprising: athird layer of the wall; depositing a metal two layer comprising: afourth layer of wall, and one or more pair of vertical frame slotssurrounding a pass-thru; depositing and patterning a third dielectriclayer comprising: one or more pairs of vertical frames and a top frame;depositing a metal three layer comprising: a fifth layer of the wall anda lid.
 12. The method of constructing an apparatus on a wafer of claim11, comprising: one or more of the vertical frame pairs; and one or moreof the top frames are voids filled with air.
 13. The method ofconstructing an apparatus on a wafer of claim 11, wherein further layersof dielectric and metals are deposited to form additional insulatedpass-thrus at different levels.
 14. The method of constructing anapparatus on a wafer of claim 13, comprising: one or more of thevertical frame pairs; and one or more of the top frames are voids filledwith air.
 15. A method of constructing an apparatus on a wafer,comprising: depositing and pattern etching a first dielectric layer overone or more semiconductor devices comprising: first via openingsexposing the semiconductor devices, and a first slot that surrounds theone or more semiconductor devices; depositing and polishing a firstconducting material to form first vias in the first via openings and afirst layer of a wall in the first slot; depositing and pattern etchinga metal one layer comprising: first interconnects and a second layer ofthe wall positioned over the first layer of the wall; depositing andpattern etching a second dielectric layer comprising: second viaopenings that expose a portion of the first interconnects, a second slotpositioned over the second layer of the wall, and one or more baseframes within the second slot; depositing and polishing a secondconducting material to form second vias in the second via openings and athird layer of the wall in the second slot; depositing and patternetching a metal two layer comprising: second interconnects, a fourthlayer of the wall positioned over the third layer of the wall, and apair of vertical frame slots on each of the one or more base frames andeach surrounding the pass-thru therein; depositing and pattern etching athird dielectric layer comprising: vertical frame pairs; a third slotpositioned over the fourth layer of the wall, and top frames locatedover the vertical frame pairs; depositing a metal three layer to form: afifth layer of the wall in the third slot, and a lid.
 16. The method ofconstructing an apparatus on a wafer of claim 15, comprising: one ormore of the vertical frame pairs; and one or more of the top frames arevoids filled with air.
 17. The method of constructing an apparatus on awafer of claim 15, wherein further layers of dielectric and metals aredeposited to form additional insulated pass-thrus at different levels.